The invention relates generally to electronic memory. More particularly, the invention relates to an apparatus and method for generating a write current for a magnetic memory cell.
Non-volatile memory is memory that retains its content (data) even when power connected to the memory is turned off. Magnetic random access memory (MRAM) is a type of non-volatile memory. MRAM includes storing a logical state, or bit, by setting magnetic field orientations of MRAM cells within the MRAM. The magnetic field orientations remain even when power to the MRAM cells is turned off.
FIG. 1 shows an MRAM cell 100. The MRAM memory cell 100 includes a soft magnetic region 120, a dielectric region 130 and a hard magnetic region 110. The orientation of magnetization within the soft magnetic region 120 is non-fixed, and can assume two stable orientations as shown by the arrow M1. The hard magnetic region 110 (also referred to as a pinned magnetic region) has a fixed magnetic orientation as depicted by the arrow M2. The dielectric region 130 generally provides electrical insulation between the soft magnetic region 120 and the hard magnetic region 110.
The MRAM memory cell generally is located proximate to a crossing point of a word line (WL) and a bit line (BL). The word line and the bit line can be used for setting the magnetic state of the memory cell, or for sensing an existing magnetic state of the memory cell. FIG. 1 also includes a proximate word line that can also be used to set the magnetic state of the MRAM memory cell 100. A magnetic field as depicted by the arrow 150 can be induced by a current I flowing through the proximate word line. The induced magnetic field can set the magnetic state of the MRAM memory cell 100.
As previously stated, the orientation of magnetization of the soft magnetic region 120 can assume two stable orientations. These two orientations, which are either parallel or anti-parallel to the magnetic orientation of the hard magnetic region 110, determine the logical state of the MRAM memory cell 100. The soft magnetic region 120 is generally referred to as the sense or data layer, and the hard magnetic region 110 is generally referred to as the pinned or reference layer.
The magnetic orientations of the MRAM memory cells can be set (written to) by controlling electrical currents flowing through the word lines and the bit lines, and therefore, by the corresponding magnetic fields induced by the electrical currents. Because the word line and the bit line operate in combination to switch the orientation of magnetization of the selected memory cell (that is, to write to the memory cell), the word line and the bit line can be collectively referred to as write lines. Additionally, the write lines can also be used to read the logic value stored in the memory cells. The electrical currents applied to the bit line and the word line set the orientation of the magnetization of the data layer depending upon the directions of the currents flowing through the bit line and the word line, and therefore, the directions of the induced magnetic fields created by the currents flowing through the bit line and the word line.
The MRAM memory cells are read by sensing a resistance across the MRAM memory cells. The resistance is sensed through the word lines and the bit lines. Generally, the logical state (for example, a xe2x80x9c0xe2x80x9d or a xe2x80x9c1xe2x80x9d) of a magnetic memory cell depends on the relative orientations of magnetization in the data layer and the reference layer. For example, in a tunneling magneto-resistance memory cell (a tunnel junction memory cell), when an electrical potential bias is applied across the data layer and the reference layer, electrons migrate between the data layer and the reference layer through the intermediate layer (a thin dielectric layer typically called the tunnel barrier layer). The migration of electrons through the barrier layer may be referred to as quantum mechanical tunneling or spin tunneling. The logic state can be determined by measuring the resistance of the memory cell. For example, the magnetic memory cell is in a state of low resistance if the overall orientation of the magnetization in its data storage layer is parallel to the pinned orientation of magnetization of the reference layer. Conversely, the tunneling junction memory cell is in a high resistance if the overall orientation of magnetization in its data storage layer is anti-parallel to the pinned orientation of magnetization of the reference layer. As mentioned, the logic state of a bit stored in a magnetic memory cell is written by applying external magnetic fields that alter the overall orientation of magnetization of the data layer. The external magnetic fields may be referred to as switching fields that switch the magnetic memory cells between high and low resistance states.
FIG. 2 shows an array 210 of MRAM memory cells. The logical states of each of the MRAM memory cells can be magnetically set by induced magnetic fields from currents flowing through the bit lines (BL) and word lines (WL). It is critical that the magnetic fields generated by the bit lines (BL) and word lines (WL) be great enough to reliably set the orientation of magnetization of the selected memory cells of the array of MRAM memory cells 210.
Generally, the bit line and word line selections are made through a row decoder 220 and a column decoder 230. The logical states of the memory cells are determined by a sense amplifier 240.
The array 210 of MRAM memory cells can suffer from half-select errors when writing to the memory cells. Memory cells are selected by selecting a particular bit line (BL), and selecting a particular word line (WL). A half-select error occurs when a memory cell associated with a selected bit line and a non-selected word line changes states, or when a memory cell associated with a non-selected bit line and a selected word line changes states. Clearly, half-select errors degrade the performance of MRAM memory.
It is desirable to minimize half-select errors of MRAM memory cells within arrays of MRAM memory cells. Additionally, it is desirable ensure that write operations to the MRAM memory cells be consistent and reliable.
The invention includes an apparatus and method of writing to magnetic memory cells. The apparatus and method minimizes half-select errors while still providing write operations to the MRAM memory cells that are consistent and reliable.
An embodiment of the invention includes an apparatus for generating a write current for a magnetic memory cell. The apparatus includes a write current generator for generating a write current, the write current being magnetically coupled to the magnetic memory cell. The apparatus further includes at least one test magnetic memory cell, the write current being magnetically coupled to the at least one test magnetic memory cell. A switching response of the at least one test magnetic memory cell determines a magnitude of the write current generated by the write current generator.
Another embodiment of the invention includes a method for determining a write current for a magnetic memory cell. The method includes supplying a test write current to a test magnetic memory cell, sensing a magnetic state of the test magnetic memory cell to determine a switching response of the test magnetic memory cell, and generating the write current having a magnitude that is dependent upon the switching response.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.